ASML — ASML
Probably one of the best semiconductor businesses on earth. That still doesn’t mean my portfolio needs it.
ASML is the lithography bottleneck behind leading-edge chips. EUV is about as close to a technological tollbooth as semiconductors gets. I did not pass because I dislike the business. I passed because I already have a lot of the portfolio riding on the same broad semiconductor and AI capex cycle.
ASML is the annoying kind of company where I can spend an hour explaining why the moat is absurd and still end with “yeah, I’m not buying it.” EUV is a genuine bottleneck in leading-edge chip production. I was never confused about the business quality.
Why I care about this one
ASML has one of the rare technology positions where customers basically cannot choose a comparable alternative for leading-edge EUV. The installed base then creates service and upgrade revenue on top of the system economics. It is exactly the sort of business I normally want to own for a very long time.
Q2 2026 sales were €9.3B, gross margin was 54%, operating margin was 37.1%, and management raised the 2026 sales outlook to €43B–€45B. Again: there is no “ASML is broken” argument hiding here.
This is the opposite kind of rejected idea. I do not need to spend three paragraphs convincing myself ASML has a moat. It controls critical lithography technology, earns excellent margins and spends aggressively to stay several engineering problems ahead. The issue is whether adding more semiconductor/capex-cycle exposure actually improves my portfolio.
Q2 2026 · financials in EUR
Primary sources: Q2 2026 results ↗ · Q2 investor presentation ↗
Q2 mostly reinforced what I already knew: €9.3B of sales, 54% gross margin and a raised €43B–€45B FY2026 sales outlook. The business is fine. The rejection is still portfolio construction because I already carry substantial semiconductor/capex-cycle exposure.
High-NA adoption and installed-base revenue run faster than expected, EUV intensity rises across more leading-edge layers, and customer capex broadens without hurting ASML's pricing power.
Leading-edge capex slows materially, export restrictions shrink the addressable market, customers stretch tool lives or order timing, or the semiconductor cycle becomes even more correlated with the rest of my book.
Why I passed
ASML’s lithography moat is ridiculous. The problem is that another semiconductor/capital-cycle position adds correlated exposure when I already have plenty. Passing is portfolio construction, not a bearish call.
A no-allocation decision is dated, not a permanent ban. New price, new evidence or a different portfolio context can reopen the work.
ASML’s lithography moat is ridiculous. The problem is that another semiconductor/capital-cycle position adds correlated exposure when I already have plenty. Passing is portfolio construction, not a bearish call.
Valuation & scenario math
The later entry framework used roughly 45x / 40x / 35x earnings for starter / normal / aggressive entries, with a 2%–4% eventual target. I had used a somewhat tighter 38x / 34x / 30x framework earlier. I am keeping both facts in the record because frameworks evolve.
I could absolutely invent a neat five-year CAGR table now and make the page look more complete. I am not doing that. I did not preserve a clean ASML-specific EPS-growth / terminal-multiple model when the idea was active, so pretending I had one would just be fake precision with nicer formatting.
I keep the old watchlist multiples because they are part of the record. I am not pretending I have a fresh target when I do not. If I revisit ASML, the real question is whether it replaces correlated exposure rather than just piling on another phenomenal semiconductor business.
“My current view” is the output of my dated valuation framework, not a magical buy instruction. A BUY still has to beat the expected return of what I already own and the index before it gets actual money.
Historical 45x / 40x / 35x P/E framework
| Old band | Threshold | Historical 5Y check |
|---|---|---|
| Starter | 45x | Not preserved |
| Normal | 40x | Not preserved |
| Aggressive | 35x | Not preserved |
Archived framework only. I did not preserve a clean ASML-specific five-year EPS / terminal-multiple model, and I am not going to invent one after the fact just because every page looks nicer with a CAGR.
Capital allocation
Spend to keep the moat ridiculous, then return the excess. Yeah, that works for me.
R&D and capacity spending directly defend one of the strongest bottlenecks in technology. ASML can also return cash without compromising that lead. The only real deductions are the unavoidable capital intensity and the fact that semiconductor cycles are still semiconductor cycles.
Stage-relative, not some objective rating-agency grade. The number is there to force the judgment into the open. See the rubric →
What management is actually doing with the cash
ASML's best use of capital is pretty obvious: spend enough on R&D, capacity and service to keep the moat brutally expensive to copy, then return the cash it genuinely does not need. I do not have much of a company-level complaint here. The allocation problem is mine.
What would make me reconsider
A major reduction in my existing semiconductor exposure, a truly unusual valuation dislocation, or a portfolio where ASML replaces rather than adds to correlated exposure. Until then, the next dollar has better jobs.
What can break this
Then I stop looking at ASML by itself and look at the portfolio. I already have meaningful semiconductor and AI-infrastructure exposure, and a lot of those earnings still depend on the same broad capex cycle. ASML is upstream and much more monopolistic than most of them. It is still another bet on the same neighborhood.
Zero shares does not mean I think ASML is bad. It means I do not need every phenomenal company I can find sitting in the same portfolio, especially when the risk is already represented elsewhere.